| The MOS 6510 is a slightly modified MOS 6502, coming with an additional 8 bit I/O-port and 256 bytes SRAM integrated, but otherwise fully opcode compatible. In the C64, the additional features are used for address decoding and controlling the cassette port - using a standard 6502 would require additional logic in these architectures. Like its ancestor, the MOS 6510 has an 8 bit data- and 16 bit address-bus, allowing it to access a 64K address space. Although this is certainly good for an 8 bit CPU, it's not enough for the C64 - because of ROM and I/O areas, the memory map is significantly larger,
and that's where address decoding is required (se PLA below). But there was a member of the 6500-family which could, due to an 20 bit address bus and integrated memory management, access up to 1 MB RAM: the MOS 6509 used in the CBM-II series. Also interesting, btw, is this CPU's production date, which is week 20 in 1985. By that time, production of the 6510's successor MOS 8500 had already begun (using Commodore's newer HMOS-2 production process) |